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SHANGHAI, May 25 (Reuters) - Huawei on Monday unveiled a new chip-design principle it calls the Tau Scaling Law and an accompanying architecture named LogicFolding, saying the approach can sustain performance gains as traditional transistor scaling slows.
He Tingbo, president of Huaweiâs semiconductor unit and chair of its Scientist Committee, introduced the idea at the IEEE International Symposium on Circuits and Systems in Shanghai, saying Huawei has used the principle to design and mass-produce 381 chips over the past six years.
The company said LogicFolding will shorten on-chip wiring and signal delays and that its next Kirin smartphone chips due in autumn 2026 will be the first to adopt the approach.
Huawei also projected it could achieve transistor-density performance equivalent to 1.4-nanometre-class chips by 2031, a target that would approach the global frontier.
The company did not provide independent benchmark data.
Analysts note the move comes as U.S.-led export controls restrict Chinese access to extreme ultraviolet lithography and other advanced tools, complicating conventional paths to sub-5nm manufacturing.





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