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Huawei on May 25, 2026 unveiled a new semiconductor design principle, the “Tau (τ) Scaling Law”, and an associated LogicFolding architecture, saying the approach shifts emphasis from shrinking transistors to reducing signal-propagation time across circuits and systems.
He Tingbo, president of Huawei’s semiconductor arm and a long-time company executive, presented the plan at the IEEE ISCAS symposium in Shanghai.
Huawei said it has spent six years developing the approach, has designed and mass-produced 381 chips using related techniques, and will adopt LogicFolding in Kirin smartphone chips shipping in autumn 2026.
The company projects designs equivalent to 1.4‑nanometre transistor density by 2031 without access to extreme ultraviolet (EUV) lithography from ASML, a capability blocked by U.S. export controls.
Huawei provided no independent performance or yield data; analysts noted short-term gains in Shanghai chip stocks but warned of thermal, packaging and manufacturability challenges when scaling to AI datacenters.
The announcement underscores Beijing’s push for semiconductor self-reliance amid sustained U.S. export restrictions.






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